SME
Digital Logic Design
Sequential logic and flip-flops
Use this for “Find the fastest clock for a register path with tcq = 1 ns, 6 ns of logic and tₛₑₜᵤₚ = 0.5 ns.”
Diagram
Tₘᵢₙ
=
tcq
+
tlogic
+
tₛₑₜᵤₚ
=
1
ns
+
6
ns
+
0.5
ns
=
7.5
ns.
fₘₐₓ
=
1
Tₘᵢₙ
=
133.3
MHz.
D settles just as the setup window (shaded) opens before the next edge.
D’s earliest change (dashed, tcq + tcd with tcd = 0.8 ns) comes after the hold window: the hold check passes.
This is an example. Type your own values to start a new problem.
Tₘᵢₙ (ns)
=
tcq (ns)
+
tlogic (ns)
+
tₛₑₜᵤₚ (ns)
fₘₐₓ (MHz)
=
1
÷
Tₘᵢₙ (ns)
tcq (ns)
+
tcd (ns)
≥
thold (ns)
tcd is the shortest path delay: the fastest a change can get through the logic.
Formulas
Tₘᵢₙ = tcq + tlogic + tₛₑₜᵤₚ
7.5 = 1 + 6 + 0.5
fₘₐₓ
=
1,000
Tₘᵢₙ
133.3
=
1,000
7.5
Assumptions
•
Both registers share one clock with no skew, and each flip-flop takes D on the rising edge.
•
D must be steady tₛₑₜᵤₚ before the next rising edge and stay steady thold after it.
•
The hold check, tcq + tcd ≥ thold, ignores the period; datasheets give a shorter tcq for it.
Step-by-step
WE KNOW
tcq = 1 ns, tlogic = 6 ns, tₛₑₜᵤₚ = 0.5 ns, thold = 0.5 ns, tcd = 0.8 ns
FIND
shortest clock period (Tₘᵢₙ), fastest clock (fₘₐₓ)
Step 1 · Find shortest clock period (Tₘᵢₙ)
Use Tₘᵢₙ = tcq + tlogic + tₛₑₜᵤₚ
Q changes, the logic settles, and D must then wait out the setup time before the next edge.
Tₘᵢₙ = 1 + 6 + 0.5
Tₘᵢₙ = 7.5 ns
Step 2 · Find fastest clock (fₘₐₓ)
Use fₘₐₓ = 1,000 ÷ Tₘᵢₙ
The clock rate is one over the period; 1000 turns 1/ns into MHz.
fₘₐₓ
=
1,000
7.5
fₘₐₓ = 133.3 MHz
Check
Put the numbers back in. Both sides should match.
7.5 = 1 + 6 + 0.5 ✓
133.3
=
1,000
7.5
✓
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