SME
Digital Logic Design · Problem type
The steps of a state machine design
Use this for “Design a clocked circuit that outputs 1 each time it has read 101.”
Put in order
Put the steps for designing the 101 detector in order.
1
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2
?
3
?
4
?
5
?
6
?
Assumptions
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A synchronous state machine changes state only at a clock edge, so its next state depends on the present state and input.
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The state table lists, for every state and input, the next state and the output.
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Unused binary codes are states too: check that each one leads back into the real states.
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